Fig.1 - The completed
project in a small jiffy box. The green lump with two sets of wires coming
out of it is a +5V regulator (a 78L05 and a 220µF 16V electrolytic
smoothing capacitor). This lash-up allowed me to use a cheapo unregulated
multi-voltage plugpack as the power supply for this project. You could steal
+5V off the keyboard port if you don't want another plugpack under your
desk.
Parts Manifest
- 2 x 4040 (MC74HC4040) 12-bit binary ripple counter ICs
- 1 x 25-pin male D connector
- 1 x 28-pin IC socket (ZIF is best, but will quadruple the cost of the
project)
- Small piece of Veroboard
- Short length of 14-way ribbon cable
- Lots of small pieces of thin, insulated wire (I used wire-wrap wire
- I recommend it for this project because there are a lot of wire
links on the underside of that piece of Veroboard!)
- A logic probe is handy but not essential
Estimated assembly time (for competent technician) is 30-45 minutes due
to the large number of wire segments that need to be cut to size, stripped,
and soldered.
Mounting the Veroboard on top of a small jiffy box ensures that the wiring
is kept out of harm's way. It also provides a handy space to store a voltage
regulator (if required), and/or the regulator and switching transistor which
will be required to control Vpp if and when this project is extended to
accomodate writing EPROMs as well as reading them.
Control Software
Software for DOS is available online. It
was developed under and has been certified for use within OS/2 Warp (provided
IOPL=YES). It should work under most versions of DOS. This software will
NOT work inside Windows NT. |
Theory
If you examine the circuit diagram below, you'll see just how incredibly
simple this ROM reader is. The ROM is forced into "enable" state
by tying its output enable and chip select inputs low. The address is generated
using two 4040 12-bit binary counter ICs, and data is read through the data
lines of the host's parallel printer port. The host can reset both counters
simultaneously, and can clock each counter independently.
To read out an EPROM, the host first resets both counters (to 000000000000)
by asserting their reset pins, which are tied together and connected to
the _STROBE line of the parallel port. The first byte of data can then be
read off the data bus. The host then clocks the lower 4040 (IC1) by pulsing
the INIT line on the parallel port. The next byte of data can then be read
on the parallel port's data bus. This process is repeated until 2^12 counts
have been made - the upper counter is then clocked by pulsing XT. This continues
until the desired amount of data has been read.
Troubleshooting
Random corruption: Keep your hands away from the reader while
dumping ROMs. Touching the ROM, or even just bringing body parts within
a few centimeters of the reader, can corrupt the results. Also see below.
All bytes read back are the same: If the reader consistently reads
back the same byte, usually "FF", your machine's parallel port
is probably configured for SPP (unidirectional) mode. Check the CMOS setup
screen, under the "On-Board Ports", "Integrated Peripherals"
or similar heading - on modern machines you should find some options related
to parallel port settings. Ensure that your port is set to "EPP"
mode (EPP1.7 or EPP1.9 are the same. DON'T set SPP or ECP mode). If your
machine has no such CMOS setting, you need to investigate jumper settings
on the I/O card or motherboard.
Spurious clocking causing bytes to be missed: If you encounter
problems with spurious clocking, first ensure that your machine's parallel
port is NOT set to ECP mode (you will find this setting in the CMOS setup
screen on modern PCs, it will be a jumper setting on older machines). If
that isn't the solution, then put 22pF plate capacitors across the power
supply pins of the counter ICs and EPROM (for power supply decoupling),
and 33k pullup resistors on the clock and reset pins of the counter ICs
(for TTL/LS to CMOS level matching). These haven't been necessary on any
of the PCs to which I have access. |
